Sr. RTL (Verilog/VHDL) Engineer (2 – 4 Yrs Experience)

Job Summary: Constelli has an immediate opening for a Senior RTL Design Engineer in Digital Signal Processing Systems department. This is a full-time role in Hyderabad.

Key Responsibilities of the job include :
► RTL Design using Verilog or VHDL or System Verilog
► Optional Skill – Modelling (simulation) using Matlab/Python/C++/LabVIEW
► Research and study signal processing algorithms & system architectures
► Deriving implementation architectures for algorithms in HDL
► Understanding system requirements and configure suitable hardware
► Interacting with Clients & dealing with third parties
► Continuous efforts to learn & adapt new technologies and grow

Requirements:
► 2-4 years of experience in RTL Coding (Verliog/VHDL) with modular, scalable and maintainable coding style
► Experience with Xilinx Vivado/ISE and/or Altera Quartus/NiosII
► Experience with programming and testing FPGA hardware
► Bachelor/Master’s degree in ECE/EE from reputed engineering institute
► Strong basics in Electronics & Communications, Signal Processing, and RF Systems